library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity divide_16 is
    port (
        nclk_i       : in  std_logic;
        reset_i      : in  std_logic;
        nclk_div16_o : out std_logic 
    );
end divide_16;

architecture behav of divide_16 is

    signal counter : std_logic_vector(3 downto 0);

begin

    process(nclk_i)
    begin
        if(nclk_i = '0' and nclk_i'event) then
            if (reset_i = '1') then
                counter <= (others => '0');
            else
                counter <= counter + 1;
            end if;
        end if;
    end process;

    process(counter)
    begin
        if(counter = 15) then
            nclk_div16_o <= '1';
        else
            nclk_div16_o <= '0';
        end if;
    end process;

end behav;

-- vim: tabstop=4 : shiftwidth=4 : expandtab
